An Improved Delayed Signal Cancelation for Three-Phase Grid Synchronization with DC Offset Immunity

Abstract

The presence of the DC components in the grid voltage adversely affects the performance of the synchronization unit, causing oscillatory and offset errors in the estimated grid information. Several approaches were proposed to address the DC offset problem by incorporating an additional filtering stage to the synchronous reference frame phase-locked loop (SRF-PLL). Removing the DC offset using the modified delayed signal cancelation (MDSC) operator in the inner loop of the SRF-PLL shows a good DC offset elimination with a fast-dynamic response. However, neither a straightforward selection procedure for the MDSC parameters nor a general estimation technique for the grid information is provided. Hence, a generalization for the MDSC is proposed in this paper based on general mathematical expressions to cancel out the DC offset, while meanwhile estimating the grid parameters precisely and rapidly against any delay factor selection. Finally, comprehensive simulation and experimental results compared with other related PLLs are presented to demonstrate the effectiveness of the proposed work.

Keywords

• DC offset rejection
• delayed signal cancelation
• phase-locked loop