Digital/Analog Performance Optimization of Vertical Nanowire FETs Using Machine Learning

Abstract

Vertical nanowire field-effect transistors (NWFETs) have been optimized to maximize digital and analog performances using fully-calibrated TCAD and machine learning (ML) technique. Digital performance is quantified by RC delay (CggVdd/Ion, where Cgg is gate capacitance, Vdd is operation voltage, and Ion is on-state current) at the fixed off-state currents, and analog performance is quantified by the product of cut-off frequency (Ft) and transconductance efficiency (Gm/Ids). ML accurately predicted the geometry and doping parameters suggesting the best device performances. All the optimized NWFETs have larger drain diameters but smaller source diameters at the minimum of gate lengths, gate oxide thicknesses, drain junction gradients, and source/drain spacer lengths. Small source diameters are needed to tightly control the energy barrier to reduce the short-channel effects, whereas large drain diameters increase current drivability than Cgg. Small drain junction gradients increase the lateral electric field from source to drain, which increases the carrier velocity. Longer spacer lengths decrease both Ion and Cgg, but the Ion degradation is critical. These device characteristics validate the optimization results from ML, and ML-based optimization is fast and effective to maximize both digital and analog performances.

Keywords

• Machine-learning (ML)
• python
• vertical
• nanowire
• RC delay
• transconductance efficiency