Memristor Based Multi-State Shift Register Architecture

Abstract

Bio-inspiring circuit design attracts a great deal of attention among researchers in the field of electronics. Memristor has emerged not only because of their potential use in neuromorphic circuits but also because of their feasible fabrication using low-cost techniques. This research presents the use of memristors to build multi-state shift registers. Memristors are capable of storing and processing multi-state logic and design of an architecture for their use in shift register have potential applications in bio-inspired integrated circuits, telecommunication systems, cryptology, display technologies, data storage, chaotic circuits, etc. The designed shift register consists of stages with capability to store and transfer multiple bits. The number of stages can be adjusted depending on the requirements of the specific applications. Each stage of the shift register consists of two memristors for a continuous signal generation at the output of each stage. Reading and writing are executed in sequential order so that when reading operation is performed by a memristor, new data is transferred to another for writing. The amplitude of the voltage corresponds to the logic state and voltage levels are classified into logic states using comparators. For n-state logic, 2n-1 comparators are required at each stage. Yakopcic’s memristor model is used in the simulations conducted in LTSPICE. The multi-state shift register architecture provided in this research successfully stores and shifts the data in the desired logic state.

Keywords

• memristor
• resistive switching
• shift register
• multi-state logic
• integrated circuits