A Novel 4H-SiC Asymmetric MOSFET with Step Trench

Abstract

In this article, a silicon carbide (SiC) asymmetric MOSFET with a step trench (AST-MOS) is proposed and investigated. The AST-MOS features a step trench with an extra electron current path on one side, thereby increasing the channel density of the device. A thick oxide layer is also employed at the bottom of the step trench, which is used as a new voltage-withstanding region. Furthermore, the ratio of the gate-to-drain capacitance (Cgd) to the gate-to-source capacitance (Cgs) is significantly reduced in the AST-MOS. As a result, the AST-MOS compared with the double-trench MOSFET (DT-MOS) and deep double-trench MOSFET (DDT-MOS), is demonstrated to have an increase of 200 V and 50 V in the breakdown voltage (BV), decreases of 21.8% and 10% in the specific on-resistance (Ron,sp), a reduction of about 1 V in the induced crosstalk voltage, and lower switching loss. Additionally, the trade-off between the resistance of the JFET region (RJFET) and the electric field in the gate oxide (Eox) is studied for a step trench and a deep trench. The improved performances suggest that a step trench is a competitive option in advanced device design.

Keywords

• SiC MOSFET
• step trench
• figure of merit (FOM)
• crosstalk