IEEE Access (Jan 2019)

Current-Starved Cross-Coupled CMOS Inverter Rings as Versatile Generators of Chaotic and Neural-Like Dynamics Over Multiple Frequency Decades

  • Ludovico Minati,
  • Mattia Frasca,
  • Natsue Yoshimura,
  • Leonardo Ricci,
  • Pawel Oswiecimka,
  • Yasuharu Koike,
  • Kazuya Masu,
  • Hiroyuki Ito

DOI
https://doi.org/10.1109/ACCESS.2019.2912903
Journal volume & issue
Vol. 7
pp. 54638 – 54657

Abstract

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The generation of chaotic signals is relevant to a multitude of applications across telecommunications, random number generation, control, and the realization of distributed sensing systems; in addition, networks of coupled chaotic oscillators replicate diverse emergent phenomena occurring in considerably larger biological neural systems. However, to date, the generation of chaotic signals by means of complementary metal-oxide-silicon (CMOS) integrated circuits has been hampered largely by the need to implement reactive elements, and by limited flexibility. In this paper, we introduce a pure CMOS implementation of a chaos generator based on three inverter rings having lengths equal to the smallest odd prime numbers, i.e., 3, 5, and 7. These rings are cross-coupled via diodes of diverse strengths enabled through pass-gates, and the inverters in the rings are independently current-starved. Through numerical simulations and experiments, it is shown that this new topology can generate chaotic signals over at least four frequency decades. Furthermore, it is demonstrated that the experimental devices have access to a multitude of qualitatively-different dynamical behaviors as a function of the starving currents. In particular, the generation of spiking and bursting signals reminiscent of action potentials are observed, both with and without slower fluctuations which resemble field potentials. Furthermore, instances of oscillation quenching are found, wherein the circuit acts as a nonlinear amplifier yielding 1/f-like stochastic signals. This compact and flexible topology promises to become a foundational cell in the design of integrated circuits requiring area-efficient, low-power, and controllable chaos generation.

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