Challenges and Innovations in CMOS-Based 300-GHz Transceivers for High-Speed Wireless Communication

Abstract

The IEEE 802.15.3d standard, issued in October 2017, defined a high-data-rate wireless physical layer using the 252–325–GHz frequency band, also known as the 300-GHz band, enabling data rates up to 100 Gb/s. This article explores the challenges and innovations associated with realizing 300-GHz transceivers using CMOS technology, which, despite its inherent limitations in high-frequency amplification, remains a critical technology for consumer electronics. The unique advantages of CMOS, such as suitability for mass production, make it an indispensable candidate for future terahertz devices. This article discusses the challenges of implementing CMOS transceivers at such high frequencies, focusing on power amplification, phased array architectures, and low-power, high-speed demodulation circuits. The solutions presented here pave the way for making 300-GHz communication practical for widespread consumer use.

Keywords

• 300-GHz communication
• carrier recovery
• CMOS technology
• high-speed demodulation
• IEEE 802.15.3d
• low-resolution analog-to-digital conversion (ADC)