A 7L and 11L High Step-Up SCMLI Topology With Reduced Component Voltage Stress

Jagabar Sathik Mohamed Ali; Amjad Rehman Khan; Gopinath Narayanan Pandurangan; Prem Ponnusamy; Faten S. Alamri; Saeed Ali Bahaj

doi:10.1109/ACCESS.2023.3333363

IEEE Access (Jan 2023)

A 7L and 11L High Step-Up SCMLI Topology With Reduced Component Voltage Stress

Jagabar Sathik Mohamed Ali,
Amjad Rehman Khan,
Gopinath Narayanan Pandurangan,
Prem Ponnusamy,
Faten S. Alamri,
Saeed Ali Bahaj

Affiliations

Jagabar Sathik Mohamed Ali: ORCiD; Department of Electrical and Electronics Engineering, SRM Institute of Science and Technology (SRMIST), Kattankulathur Campus, Chennai, Tamil Nadu, India
Amjad Rehman Khan: ORCiD; Artificial Intelligence Data Analytics Laboratory (AIDA), College of Computer and Information Sciences (CCIS), Prince Sultan University, Riyadh, Saudi Arabia
Gopinath Narayanan Pandurangan: Department of Electrical and Electronics Engineering, SRM Institute of Science and Technology (SRMIST), Kattankulathur Campus, Chennai, Tamil Nadu, India
Prem Ponnusamy: ORCiD; Department of Electrical Engineering, St. Thomas’ College of Engineering and Technology, Kolkata, India
Faten S. Alamri: ORCiD; Department of Mathematical Sciences, College of Science, Princess Nourah bint Abdulrahman University, Riyadh, Saudi Arabia
Saeed Ali Bahaj: ORCiD; MIS Department College of Business Administration, Prince Sattam Bin Abdulaziz University, AlKharj, Saudi Arabia

DOI: https://doi.org/10.1109/ACCESS.2023.3333363
Journal volume & issue: Vol. 11
pp. 139785 – 139797

Abstract

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This article proposes a new capacitor-based multilevel inverter topology (CBMLI) with fewer devices and reduced voltage stress on capacitors and switches. In addition, the proposed topology can be configured as either a 7-level (7L) or 11L circuit with a maximum voltage gain of 3 and 2.5 times, respectively. Comparisons are made between the proposed topology and existing recent CBMLI topologies, and various power loss analyses are presented. The capacitance values are determined by selecting the maximum discharging period, and the associated analysis is presented. Using the simulation software MATLAB/Simulink, the performance of the proposed circuit topology is validated, and the same is tested in the hardware setup. The various dynamic performance characteristics, such as loading changes, input variations, and modulation index, are validated, and the resulting data is discussed.

Published in IEEE Access

ISSN: 2169-3536 (Online)
Publisher: IEEE
Country of publisher: United States
LCC subjects: Technology: Electrical engineering. Electronics. Nuclear engineering
Website: https://ieeexplore.ieee.org/xpl/RecentIssue.jsp?punumber=6287639

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