Logic‐Compatible Charge‐Trapping Tunnel Field Effect Transistors for Low‐Power, High‐Accuracy, and Large‐Scale Neuromorphic Systems

Abstract

Charge‐trapping tunnel field effect transistors (CT‐TFETs) are experimentally demonstrated, and their array operations are discussed for low‐power large‐scale neuromorphic applications. CT‐TFETs cointegrated with charge‐trapping metal–oxide–semiconductor FETs (CT‐MOSFETs) through complementary metal–oxide–semiconductor logic process exhibit ≈2,000× lower on‐current (Ion) and ≈3,000× lower off‐current (Ioff) than CT‐MOSFETs, rendering them suitable for high‐accuracy large‐scale neuromorphic systems. According to the experimental and simulation results, CT‐TFETs outperform CT‐MOSFETs in terms of more accurate analog vector‐matrix multiplication than that of CT‐MOSFETs due to the following two reasons: first, CT‐TFETs feature a lower voltage (IR) drop resulting from lower Ion than that of CT‐MOSFETs. Second, the former is more robust to the IR drops than the latter due to weak channel length modulation. For example, unlike CT‐MOSFETs, the proposed CT‐TFETs exhibit ignorable weight degradation in spite of the 1 Ω wire resistance. CT‐TFET arrays show ≈700× lower power consumption and ≈10% higher MNIST classification accuracy than CT‐MOSFET arrays, making CT‐TFET arrays promising for extensive and versatile neuromorphic computing applications.

Keywords

• charge-trapping TFETs
• lower voltage drop
• neuromorphic hardware architectures