A Negative-Feedback Gate-Loop for Current Balancing Paralleled SiC MOSFETs Based on a Differential Mode Inductor

Abstract

Using paralleled SiC MOSFETs is an economical and commonly-used solution for high-power applications. However, the dynamic unbalanced currents during TURN-ON and TURN-OFF processes can pose the security and stability threats in the parallel connection of SiC MOSFETs. To address this issue, this article proposes a current balancing method for paralleled SiC MOSFETs by adding a Differential Mode Inductor (DMI) at the source terminals. Each DMI connects the primary and secondary sides to the source terminals of two SiC MOSFETs respectively. Without requiring voltage/current sensors or feedback control, a negative feedback gate-loop for balancing the currents of paralleled SiC MOSFETs is established through the gate-source voltages, which are regulated by the induced voltages of the DMI. The effectiveness of the proposed method is experimentally verified on two- and three-paralleled SiC MOSFETs. The results demonstrate that with the proposed method during turn-on process, the unbalanced currents can reduce from 26.51% to 3.08% for two-paralleled SiC MOSFETs, and from 32.97% to 8.34% and 3.67% for three-paralleled SiC MOSFETs with Open-Chain (OC) and Daisy-Chain (DC) structures respectively.

Keywords

• Paralleled SiC MOSFETs
• current balancing
• differential mode inductor
• source terminal