Degradation-Sensitive Control Algorithm Based on Phase Optimization for Interleaved DC–DC Converters

Abstract

As the use of interleaved DC–DC converters in electric vehicles (EVs) increases, research on reliability improvement is required. In the case of interleaved DC–DC converters, degradation occurs between transistors and capacitors. In particular, transistor degradation imbalances cause an increase in output capacitor RMS current, which increases power loss and accelerates capacitor degradation. This degradation affects system reliability by increasing thermal stress. In this paper, based on a degraded 2-leg interleaved DC–DC boost converter, research to reduce the converter’s output capacitor RMS current was conducted. The output capacitor RMS current according to the transistor degradation imbalance was analyzed. As a result, it was confirmed that the transistor degradation imbalance causes an increase in the capacitor RMS current. To address this issue, a phase optimization algorithm for reducing increased capacitor RMS current is presented in this paper. Next, the phase optimization algorithm is mathematically analyzed. Finally, its efficacy is proved through simulations and experiments.

Keywords

• silicon carbide MOSFET
• degradation
• 2-leg interleaved DC–DC boost converter
• capacitor RMS current
• phase optimization