A New Model for Enhancing Efficiency in On-Chip Optical ‎Networks Based on Adaptive Routing Algorithm.‎

Abstract

The lower power consumption, larger communication bandwidth, and reduced latency are advantages of optical networks over electrical communications. However, there are challenges in these networks, such as routing and connectivity issues, which result in increased network size and wastage. As networks become more complex and larger, building on-chip networks brings problems like communication costs between components and the likelihood of unpredictable failures in communication circuits. Therefore, providing an error-tolerant routing algorithm plays a crucial role in the development of on-chip network architecture. In this article, an adaptive fault-tolerant routing algorithm will be presented, whose main objective is to create the ability to handle a reasonable number of faults without disrupting the healthy nodes in the network. The simulation results of message delay in the proposed method show a gradient norm equal to 1.1691E-5 and μ = 1E-8 for epoch=280, demonstrating its capability to reduce delay in the network. A very slight change in message delay in evaluating the proposed method also indicates the acceptability of the proposed method. Moreover, the presence of a gradient of 1.527E-3 and μ = 1E-7 for epoch=350 in the energy consumption value indicates a reduction in energy consumption compared to conventional methods in existing references, although the proposed system may incur additional overhead compared to some previous methods.

Keywords

• adaptive routing algorithm
• congestion-aware dynamic routing
• network on-chip
• fault-tolerant algorithm