Engineering Science and Technology, an International Journal (Jun 2022)
Low latency high throughput Montgomery modular multiplier for RSA cryptosystem
Abstract
With the advancements of communication technology, security threats are also increasing. RSA is a robust cryptosystem to protect classified information. The efficiency of RSA cryptosystem depends on the efficient execution of Montgomery modular multiplication. A low latency and throughput efficient Montgomery modular multiplier is proposed in this paper. The input and final output of this multiplier are binary, but intermediate input and output are carry-saved i.e. sum and carry bits are stored in separate registers. Sum and carry bits are obtained from the addition of operands using carry-save adder (CSA). Montgomery multipliers require quotient calculation for subsequent iteration. The proposed multiplier computes two subsequent quotients in parallel with carry-save addition. Output of carry-save addition is right shifted by two bits to obtain the next-to-next intermediate output. This calculation also requires integer multiples of the inputs. Computation of next output is skipped. Format conversion of output is performed using a carry look-ahead unit (CLU). CLU along with one cycle of carry save addition is also utilized for pre-computation of integer multiples of inputs. The proposed multiplier is implemented on NEXYS4DDR and VIRTEX VII FPGA and the following result is obtained. NEXYS4DDR: Area (LUT + REG): 38903, Delay: 5.84 ns, Cycles: 1158, Latency: 6.76 µs, Throughput: 302.96 Mbps. VIRTEX VII: Area (LUT): 16447, Delay: 1.62 ns, Cycles: 1158, Latency: 1.88 µs, Throughput: 1089.4 Mbps. Results verify the improved area, latency and throughput performance of the proposed work.
