A New Systolic Array Algorithm and Architecture for the VLSI Implementation of IDST Based on a Pseudo-Band Correlation Structure

Abstract

In this paper a new linear VLSI array architecture for the VLSI implementation of a prime-length 1-D Inverse Discrete Sine Transform (IDST) is proposed. This new design approach uses a new efficient VLSI algorithm based on a regular and modular computational structure called pseudo-band correlation structure. It employs a new formulation of the inverse DST that is mapped on a linear systolic array. Using the proposed systolic array high computing speed is obtained with a low hardware complexity and low I/O cost. A highly efficient VLSI chip can be obtained characterized by a small number of I/O channels located at the two extreme ends of the array together with a low I/O bandwidth that is independent of the transform length N, a good topology with modular, regular and local connections.

Keywords

• discrete transforms
• digital integrated circuits
• field programmable gate arrays
• large scale integration
• systolic arrays