Design and Implementation of a Generalized N-Digit Binary-To-Decimal Converter on an FPGA Seven-Segment Display Using Verilog Hdl

Abstract

It is often needed to have circuits that can display the decimal representation of a binary number and specifically in this paper on a 7-segment display. In this paper a circuit that can display the decimal equivalent of an n-bit binary number is designed and it’s behavior is described using Verilog Hardware Descriptive Language (HDL). This HDL program is then used to configure an FPGA to implement the designed circuit.

Keywords

• binary to decimal converter, FPGA, Verilog HDL, seven segment display, Cyclone II de1 board.