Evaluation of Temperature, Disturbance and Noise Effect in Full Adders Based on GDI Method

Abstract

In this paper, we limit our attention to full adders based on the GDI method, circuits that are commonly used in high-speed circuits and are more prone to noise. So far, a comprehensive review on noise immunity and ambient temperature change of full adders based on the GDI method has not been presented, and most of the studies have compared their proposed design with other full adders, which are mainly not based on the GDI method. These full adder cells were evaluated by various simulations such as supply voltage change, capacitive load change, ambient temperature change and process-voltage-temperature (PVT) changes in 45 nm CMOS technology. A noise immunity curve (NIC) was derived for full adder cells to identify better-performing full adder cells. The unity noise gain (UNG) was also investigated to evaluate the noise. Finally, a comprehensive comparison was made in terms of propagation delay, power consumption, power-delay product (PDP), voltage swing, sensitivity to process changes and noise for full adders based on the GDI method. The obtained results can be useful in the decisions of integrated circuit designers to choose the appropriate structure of the full adder based on the GDI method

Keywords

• noise immunity curve (nic)
• gdi method
• power-delay product (pdp)
• unity noise gain (ung)
• full adder