Machine Learning Integrated Pseudo-3-D Flow for Monolithic 3-D ICs

Abstract

Monolithic 3-D (M3-D) IC design is a manufacturing technique that opens several new possibilities of chip design and exploration for power, performance, area (PPA), and cost benefits. Designing a commercially viable M3-D IC first requires a sign-off timing closure capability. Since the commercial tools lack such capability, several 3-D flows have been proposed that treat 3-D as a 2-D die and use commercial 2-D electronic design automation (EDA) tools for the RTL-to-GDS stage. The conversion between the two stages is done late in the design flow and the conversion is also nontrivial. Here, we propose a machine learning-based prediction algorithm to decrease the discrepancy between the pre and post-partitioned 3-D design using regression models. Our proposed model is circuit-agnostic and its performance with respect to a circuit-dependent model is also studied. Furthermore, more details on the behavior and analysis of the model are considered. Overall, we achieve a significant reduction in the total negative slack (TNS) of the test design ( $3\times $ – $16\times $ ) using the machine learning model integrated pseudo-3-D flow at an expense of just −1%–4% increase in total power.

Keywords

• Interconnect analysis
• monolithic 3-D (M3-D) IC
• pseudo-3-D Flows
• tier partitioning