Frontiers in Materials (Feb 2016)
Gate-stack engineering for self-organized Ge-dot/SiO2/SiGe-shell MOS capacitors
Abstract
We report the first-of-its-kind, self-organized gate-stack heterostructure of Ge-dot/SiO2/SiGe-shell on Si fabricated in a single step through the selective oxidation of a SiGe nano-patterned pillar over a Si3N4 buffer layer on a Si substrate. Process-controlled tunability of the Ge-dot size (7.5−90 nm), the SiO2 thickness (3−4 nm), and as well the SiGe-shell thickness (2−15 nm) has been demonstrated, enabling a practically-achievable core building block for Ge-based metal-oxide-semiconductor (MOS) devices. Detailed morphologies, structural, and electrical interfacial properties of the SiO2/Ge-dot and SiO2/SiGe interfaces were assessed using transmission electron microscopy, energy dispersive x-ray spectroscopy, and temperature-dependent high/low-frequency capacitance-voltage measurements. Notably, NiGe/SiO2/SiGe and Al/SiO2/Ge-dot/SiO2/SiGe MOS capacitors exhibit low interface trap densities of as low as 3-5x10^11 cm^-2·eV^-1 and fixed charge densities of 1-5x10^11 cm^-2, suggesting good-quality SiO2/SiGe-shell and SiO2/Ge-dot interfaces. In addition, the advantage of having single-crystalline Si1-xGex shell (x > 0.5) in a compressive stress state in our self-aligned gate-stack heterostructure has great promise for possible SiGe (or Ge) MOS nanoelectronic and nanophotonic applications.
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