Topological Horseshoe Analysis and FPGA Implementation of a Classical Fractional Order Chaotic System

Abstract

Scholars have done extensive research on dynamic analysis and analog circuits implementation of the classical fractional order chaotic system-Liu System (FOLS). However, they did not rigorously prove the existence of FOLS from the perspective of mathematics. And they also did not effectively design digital circuits to generate signals of the fractional order chaotic systems, especially the 2.7-order system. This paper selects an appropriate Poincaré section where a first return Poincaré map of FOLS was defined. Based on computer-assisted verification method, the conclusion is that the Poincaré map is semi-conjugate to a 2-shift map and the topological entropy of the map is no less than ln 2, which rigorously verifies the existence of chaotic behavior in the 2.7-order Liu system. This proof is necessary before the chaotic system is used for information encryption. The next and most significant task is to build a system model through DSP-Builder software and generate chaotic signals using Field Programmable Gate Array chip. The results of oscilloscope consistent with numerical simulations, which lays the foundation for image and video streaming encryption.

Keywords

• Computer-assisted proof
• fractional order liu System
• FPGA implementation
• topological horseshoe analysis