Dual segmentation approximate multiplier

Abstract

Abstract This letter proposes a new design for a dual segmentation approximate multiplier. The proposed approximate multiplier uses the static segment method (SSM) to select an initial multiplication segment. Following that, the dynamic segment method (DSM) is utilized to further reduce the initial segment size. Using only the DSM segmenter leads to reduced performance gains. Therefore, the proposed multiplier uses a mixture of the SSM and DSM approaches. Compared to the DSM approach, the proposed design can reduce the energy by 37.90% for 32‐bit multipliers, and by 16.68% for 16‐bit multipliers. The DSM and proposed multipliers have almost identical accuracy.

Keywords

• Digital circuit design, modelling and testing
• Logic circuits
• Logic and switching circuits
• Logic design methods