Fast Regular Circuits for Network-based Parallel Data Processing

Abstract

This paper is dedicated to the design, implementation, and evaluation of fast circuits executing operations that are frequently required in data processing which are: 1) discovering the maximum and minimum values in a given set of data; and 2) sorting data items. We found that minimizing the number of circuit components does not guarantee minimal hardware resources. This is because interconnections also influence the complexity significantly. Network-based circuits are often considered to be combinational. However, this does not mean that they are faster than sequential circuits solving the same problem because propagation delays can be considerable. We revised the existing network-based solutions and proposed regular circuits which provide a good compromise between hardware resources and performance.

Keywords

• data processing
• field-programmable gate arrays
• parallel processing
• reconfigurable architectures
• sorting