Strained Si Nanosheet pFET Based on SiC Strain Relaxed Buffer Layer for High Performance and Low Power Logic Applications

Abstract

The application of SiC-based strain-relaxed buffers (SRB) technology in gate-all-around (GAA) pMOS nanosheet transistors (NS-FETs) fabrication has been systematically investigated. TCAD simulation results show that SiC SRB can effectively enhance the p-channel stress, up to 3.8Gpa has been achieved without S/D parasitic RC degradation. Furthermore, introducing a wide-bandgap SiC layer underneath NS-FET can help suppress the bottom parasitic transistor. The SiC SRB technology presents a integrated and streamlined approach for addressing the major performance bottlenecks of NS-FETs and is a potential solution for developing future NS-FET based high-performance and low-power logic applications.

Keywords

• Gate-all-around (GAA)
• nanosheet (NS-FET)
• S/D stressor
• stress enhancement
• strain relaxed buffer