Analysis and Design of FeFET Synapse With Stacked-Nanosheet Architecture Considering Cycle-to-Cycle Variations for Neuromorphic Applications

Abstract

Using extensive Monte-Carlo simulations with a nucleation-limited-switching (NLS) ferroelectric model and considering cycle-to-cycle variations, this paper constructs and analyzes the intrinsic conductance (GDS) response of stacked-nanosheet FeFET synapses with emphasis on the challenging identical-pulse stimulation. Our study indicates that the interlayer oxide thickness of the FeFET and the saturation polarization of the ferroelectric are crucial to the linearity and symmetry of the intrinsic GDS response. With the stacked-nanosheet architecture, the maximum-to-minimum conductance ratio in the GDS response can be boosted by increasing the number of channel tiers without footprint penalty. For a stacked-nanosheet FeFET synapse with an area ratio effect, the GDS response can be further engineered by varying the tier number. In addition, the immunity to cycle-to-cycle variations and the noise margin for each state in the GDS response can also be improved by increasing the number of tiers. Our study may provide insights for future FeFET synapse design for analog computing.

Keywords

• Stacked nanosheet
• ferroelectric field-effect transistor (FeFET)
• analog synapse
• neuromorphic computing