An Energy-Efficient Pipeline-SAR ADC Using Linearized Dynamic Amplifiers and Input Buffer in 22nm FDSOI

Abstract

Recently, dynamic amplifier (DA) has emerged as a popular alternative to static current closed-loop operational transconductance amplifier (OTA) due to their highly power-efficient integration-based settling, with the main limitation being their linearity performance. We present a DA that achieves −52 dB in total harmonic distortion (THD) through an analog technique by which the expanding and compressing nonlinearities in the input transistors cancel one another. A pipeline-SAR analog-to-digital converter (ADC) incorporating the linearized DA in both the input buffer and the first residue amplifier (RA) stage was designed and fabricated using the GlobalFoundries 22nm fully depleted silicon-on-insulator (FDSOI) process. Measurements showed the ADC achieved a signal-to-noise-distortion ratio (SNDR) of 37 dB at 920 MS/s consuming a total power of 1.8mW for a Walden FOM (FOMW) of 34.9 fJ/conv. With the input buffer, the achieved FOMW is 68.4 fJ/conv. The linearization technique provided a 8 dB improvement in SNDR at its optimal biasing with a negligible power overhead of approximately 5%. In general, it is expected that an 8 dB SNDR improvement would require 2.5 times the power consumption for a mismatch-limited design (Walden FOM) or 6.3 times the power for a noise-limited design (Schreier FOM).

Keywords

• Analog-to-digital converter (ADC)
• dynamic amplifier
• pipelined-SAR
• linearity
• fully depleted silicon-on-insulator (FDSOI)