A 10 GHz Dual-Loop PLL With Active Cycle-Jitter Correction Achieving 12dB Spur and 29% Jitter Reduction

Abstract

This paper presents the design of a 10 GHz dual-loop PLL with active cycle-jitter correction. In the main loop of the PLL, a sampling PD is utilized to suppress the in-band noise to reach the reference noise floor. On the other hand, to eliminate noise disturbance outside the PLL loop bandwidth, an active cycle-jitter correction (ACJC) loop is proposed and incorporated in this design. The ACJC utilizes a delay-discriminator based cycle jitter extractor and is performed at the subharmonic of VCO. It provides jitter suppression far beyond a conventional PLL loop bandwidth. An experimental prototype has been fabricated in a TSMC 40 nm CMOS process. By activating the ACJC, the spurious tones can be reduced by 12 dB when a 260MHz disturbance is injected without resort to sophisticated calibration. The integrated jitter from 1kHz to 260 MHz can be reduced from 413.7 fs to 293.21 fs, which corresponds to 29% improvement in jitter reduction. The PLL core consumes 22.1 mW. The chip area is about 0.97x0.96 mm2.

Keywords

• Sampling-based PD (SPD)
• sub-sampling PD (SSPD)
• active cycle-jitter correction (ACJC)