Novel Dual Work Function Buried Channel Array Transistor Process Design for Sub-17 nm DRAM

Abstract

This paper introduces the smallest dynamic random access memory (DRAM) cell, which was implemented using a new transistor structure, the dual work function - buried channel array transistor (DWF-BCAT). For the first time, a feature size of approximately 17 nm was achieved for a DRAM cell. In this study, a novel cell gate oxide process that mitigates traps in the gate oxide and gate interface, whose dimensions scale concurrently, was developed to fabricate the DWF-BCAT. By utilizing a three-step process involving in-situ steam generation (ISSG) followed by atomic layer deposition (ALD) then another cycle of ISSG (IAI) to create the dual work function gate, a significant improvement in DRAM data retention characteristics is achieved. A new barrier fabrication process called plasma nitridation treatment of oxide film (PNOF) was also developed. Oxide film barriers for two gate materials, namely tungsten and polycrystalline Si, were deposited using PNOF. Device characterization results reveal that PNOF is highly effective in reducing interfacial resistance by suppressing the inter-diffusion of gate materials, leading to improved DRAM write time characteristics. Additionally, gate oxide defects can be repaired and surface contamination can be removed by applying an HF wet strip (HFWS) process. The BCAT design and fabrication strategies applied in this study can accelerate the miniaturization of DRAMs toward the theoretical scaling limit.

Keywords

• Dual work function-buried channel array transistor (DWF-BCAT)
• IAI
• PNOF
• HFWS