Power Gating Technique for Power Reduction and Data Retention in CMOS Circuits

Abstract

Usage of battery powered hand held devices has been increasing in this modern era. To extend the battery life of these devices, more aggressive power reduction techniques are necessary. Power gating techniques are commonly used for suppressing leakage in digital VLSI circuits. In this paper a power gating technique is proposed for efficient leakage reduction and data retention. The simulation results reveal that the proposed technique exhibits 84-93% leakage reduction, 7-28% drowsy power reduction, 4-30% dynamic power reduction compared to conventional technique. Proposed technique also provides good data stability than existing technique.

Keywords

• leakage power
• power gating
• data retention
• drowsy mode
• charge recycling
• stack effect