Analysis of Power-Supply-Rejection Enhancement Techniques for Low-Dropout Regulators

Abstract

This article presents a comprehensive analysis of power-supply-rejection (PSR) enhancement techniques in low-dropout regulators (LDOs) for efficient power management within system-on-chips (SoCs). The PSR is a critical performance metric for LDOs, as it ensures the suppression of power supply ripple and provides stable output voltages. Various PSR enhancement techniques aimed at enhancing PSR characteristics have been proposed, and this study endeavors to offer insights by analyzing these techniques. PSR enhancement techniques can be broadly categorized into two main categories: supply ripple insensitivity/bandwidth improvement and feedforward supply ripple cancellation (FFRC). Supply ripple insensitivity techniques involve the use of a cascading LDO to pre-regulate the supply ripple in the main LDO loop, and bandwidth improvement techniques focus on improving the ripple suppression bandwidth of the LDO. FFRC techniques aim to mitigate the supply ripple by injecting supply ripple through a feedforward path. In addition to analyzing PSR enhancement techniques, this article discusses recent research trends through a performance comparison. Furthermore, it provides valuable insights into the design and optimization of LDOs for PSR enhancement.

Keywords

• Low-dropout regulator (LDO)
• power management unit (PMU)
• power-supply-rejection (PSR)
• PSR enhancement
• feedforward supply ripple cancellation (FFRC)