FPGA-based low-light image enhancement using Retinex algorithm and coarse-grained reconfigurable architecture

Abstract

Abstract Advancements in digital imaging and video processing are often challenged by low-light environments, leading to degraded visual quality. This affects critical sectors such as medical imaging, aerospace, and underwater exploration, where uneven lighting can compromise safety and clarity. To enhance image quality in low-light conditions using a computationally efficient system. This paper introduces an FPGA-based system utilizing the Retinex algorithm for low-light image enhancement, implemented on a Coarse-Grained Reconfigurable Architecture (CGRA). The system is designed using Verilog HDL on a Xilinx FPGA, prioritizing hardware optimization to achieve high-quality outputs with minimal latency. The system achieves a processing rate of 60 frames per second (fps) for images with a resolution of 720 × 576. Quantitative evaluations show a Peak Signal-to-Noise Ratio (PSNR) improvement to 43.18 dB, a Structural Similarity Index (SSIM) of 0.92, and a Mean Squared Error (MSE) reduction, demonstrating significant enhancements in image quality. The design also achieves a low power consumption of 0.186 W and efficient resource utilization, with only 2.2% of Slice LUTs and Slice Registers used. The FPGA-based system demonstrates significant improvements in image quality with high computational efficiency, proving beneficial for critical applications in various sectors.

Keywords

• CGRA
• FPGA
• Low-light enhancement
• Retinex
• Image processing
• Gaussian filter