Design and implementation of codec based on BCH error correction algorithm

Abstract

With the rapid development of NAND Flash memory cells and the increase in storage density, the error probability of devices has increased. For this reason, an optimized BCH codec structure is proposed. The encoding and decoding process can process 16-bit data in parallel in each clock cycle. Among them, the syndrome module, error location polynomial module and Chien search module in the decoding circuit adopt a three-stage pipeline structure, and the error correction and error detection stages can be carried out at the same time, which effectively improves the data processing speed and error correction speed. After completing the RTL design of the circuit, the simulation verification of the circuit was completed by using the VCS tool. The results showed that 48-bit error correction was achieved when 8 192 bit data was transmitted to generate 672 check factors, and the maximum operating frequency was 200 MHz.

Keywords

• nand flash
• bch code
• chien search
• pipeline structure
• codec