Ultra-Low Static Power Circuits Addressing the Fan-Out Problem of Analog Neuron Circuits in Spiking Neural Networks

Abstract

In hardware-based spiking neural network (SNN) systems, neuron circuits face significant fan-out issues owing to their massively parallel connections to post-synaptic arrays, leading to distortion in the output spikes. This not only affects spike generation rates but also causes read voltage drops in post-synaptic arrays, ultimately degrading the system’s accuracy. Previous solutions to the fan-out problem, including the incorporation of delay-capacitors, inverter chains, or operational amplifiers, require substantial area and consume considerable static power, thereby impeding low-power computing for event-driven operations in SNN. To address this issue, we propose the integration of spike-based voltage buffers (S-VBs) and pull-down pulse width modulation (PD-PWM) circuits. The proposed circuits operate in a fully event-driven manner, resulting in a very low static power consumption. Remarkably, the PD-PWM circuit consumes less than 1 % of the energy required by the conventional delay-capacitor method for spike-width modulation. When simulated with a $512\times 512$ scale post-synaptic resistive random-access memory array, the neuron circuit with proposed fan-out circuits demonstrated an energy consumption of 447 pJ/spike, including the power to drive the synaptic arrays. In addition, the proposed fan-out circuit enables low-power operation, even at low firing rates, owing to its ultra-low static power consumption. Furthermore, system-level simulations indicate that the proposed circuit maintains high accuracy, with a drop in accuracy of less than 0.1 %p, even with a 10-%p fluctuation in the driving voltage.

Keywords

• Fan-out
• neuron circuits
• static power
• spiking neural networks