CMOS voltage‐controlled oscillator using inductive dual‐balance source degeneration

Abstract

Abstract This study reports a voltage‐controlled oscillator (VCO) implemented in a 0.18‐μm CMOS process. By utilizing an inductive dual‐balance source degeneration (IDSD) technique with a current‐reused structure, the proposed VCO improves the phase noise and the power dissipation. The measured output frequency operates at 2.91–3.07 GHz by adjusting a control voltage from 0 to 1.1 V. The measured phase noise of the carrier of 2.94 GHz is −117.44 and −138.34 dBc/Hz at 1‐ and 10‐MHz offsets, respectively. The proposed VCO core consumes 2.38 mW from a supply voltage of 1.1 V. The figures‐of‐merits (FOMs) of the proposed VCO at 1‐ and 10‐MHz offsets are −183.04 dBc/Hz and −183.94 dBc/Hz, respectively.