FEOL Monolithic Co-Integration of FeFET and CMOS on 8-Inch Wafer Using Laser Spike Annealing With Implementation of an FeFET Inverter

Abstract

Ferroelectric devices and monolithic three-dimensional integration technology (M3D) with good CMOS process compatibility have emerged as promising solutions to scaling issue at the device and system levels, respectively. In this study, we developed a monolithic co-integration scheme, which sequentially fabricates CMOS devices and ferroelectric field-effect transistors (FeFETs) on the front-end-of-line (FEOL) area of the same 8-inch wafer. To fabricate FeFETs after CMOS device fabrication and achieve co-integration on the FEOL area, an etch-back process was developed to remove thick oxide over a wide area. FeFET fabrication involves the selective laser spike annealing (LSA) in the source/drain region of the FeFET to implement the low thermal budget process crucial for monolithic integration. In our test, LSA resulted in a lower sheet resistance compared to conventional rapid thermal annealing (RTA), thus validating its performance for dopant activation. The monolithic co-integration completed by incorporating this LSA was evaluated by measuring the electrical characteristics of CMOS, FeFET and FeFET inverter, which was first fabricated in this work. By developing this monolithic co-integration, this work offers an opportunity to integrate diverse new devices in addition to the FeFET with CMOS and achieve further advancements in technology.

Keywords

• Co-integration
• FeFET inverter
• ferroelectric field-effect transistor (FeFET)
• front-end-of-line (FEOL)
• laser spike annealing
• monolithic integration