Tailoring lithium intercalation pathway in 2D van der Waals heterostructure for high‐speed edge‐contacted floating‐gate transistor and artificial synapses
Jun Yu,
Jiawei Fu,
Hongcheng Ruan,
Han Wang,
Yimeng Yu,
Jinpeng Wang,
Yuhui He,
Jinsong Wu,
Fuwei Zhuge,
Ying Ma,
Tianyou Zhai
Affiliations
Jun Yu
State Key Laboratory of Materials Processing and Die and Mould Technology, School of Material Science and Engineering Huazhong University of Science and Technology (HUST) Wuhan the People's Republic of China
Jiawei Fu
Hubei Yangtze Memory Laboratory, School of Integrated Circuits Huazhong University of Science and Technology (HUST) Wuhan the People's Republic of China
Hongcheng Ruan
School of Information Engineering Zhongnan University of Economics and Law Wuhan the People's Republic of China
Han Wang
State Key Laboratory of Materials Processing and Die and Mould Technology, School of Material Science and Engineering Huazhong University of Science and Technology (HUST) Wuhan the People's Republic of China
Yimeng Yu
State Key Laboratory of Advanced Technology for Materials Synthesis and Processing, Nanostructure Research Center Wuhan University of Technology Wuhan the People's Republic of China
Jinpeng Wang
State Key Laboratory of Materials Processing and Die and Mould Technology, School of Material Science and Engineering Huazhong University of Science and Technology (HUST) Wuhan the People's Republic of China
Yuhui He
Hubei Yangtze Memory Laboratory, School of Integrated Circuits Huazhong University of Science and Technology (HUST) Wuhan the People's Republic of China
Jinsong Wu
State Key Laboratory of Advanced Technology for Materials Synthesis and Processing, Nanostructure Research Center Wuhan University of Technology Wuhan the People's Republic of China
Fuwei Zhuge
State Key Laboratory of Materials Processing and Die and Mould Technology, School of Material Science and Engineering Huazhong University of Science and Technology (HUST) Wuhan the People's Republic of China
Ying Ma
State Key Laboratory of Materials Processing and Die and Mould Technology, School of Material Science and Engineering Huazhong University of Science and Technology (HUST) Wuhan the People's Republic of China
Tianyou Zhai
State Key Laboratory of Materials Processing and Die and Mould Technology, School of Material Science and Engineering Huazhong University of Science and Technology (HUST) Wuhan the People's Republic of China
Abstract Local phase transition in transition metal dichalcogenides (TMDCs) by lithium intercalation enables the fabrication of high‐quality contact interfaces in two‐dimensional (2D) electronic devices. However, controlling the intercalation of lithium is hitherto challenging in vertically stacked van der Waals heterostructures (vdWHs) due to the random diffusion of lithium ions in the hetero‐interface, which hinders their application for contact engineering of 2D vdWHs devices. Herein, a strategy to restrict the lithium intercalation pathway in vdWHs is developed by using surface‐permeation assisted intercalation while sealing all edges, based on which a high‐performance edge‐contact MoS2 vdWHs floating‐gate transistor is demonstrated. Our method avoids intercalation from edges that are prone to be random but intentionally promotes lithium intercalation from the top surface. The derived MoS2 floating‐gate transistor exhibits improved interface quality and significantly reduced subthreshold swing (SS) from >600 to 100 mV dec–1. In addition, ultrafast program/erase performance together with well‐distinguished 32 memory states are demonstrated, making it a promising candidate for low‐power artificial synapses. The study on controlling the lithium intercalation pathways in 2D vdWHs offers a viable route toward high‐performance 2D electronics for memory and neuromorphic computing purposes.
