An Energy-Efficient High-Throughput Mesh-Based Photonic On-Chip Interconnect for Many-Core Systems

Abstract

Future high-performance embedded and general purpose processors and systems-on-chip are expected to combine hundreds of cores integrated together to satisfy the power and performance requirements of large complex applications. As the number of cores continues to increase, the employment of low-power and high-throughput on-chip interconnect fabrics becomes imperative. In this work, we present a novel mesh-based photonic on-chip interconnect, named PHENIC-II, for future high-performance many-core systems. The novel architecture is based on an energy-efficient non-blocking photonic switch and a contention-aware routing algorithm. Simulation results show that the proposed system provides better bandwidth and energy efficiency when compared to conventional hybrid photonic NoC systems.

Keywords

• energy efficient
• contention aware
• photonic NoC
• non-blocking photonic switch
• path-configuration
• many-core SoCs
• high-performance