An all-passive Si3N4 optical row decoder circuit for addressable optical RAM memories

Abstract

In this work we experimentally demonstrate a Si _3 N _4 photonic integrated circuit which offers row decoding and RAM addressing functionalities. The passive integrated structure comprises a MRR-based wavelength filtering bank scheme in a 2 × 4 configuration, which reveals a suppression ratio in the range of 12–25 dB. The performance of the optical circuit has been evaluated in a system-level testbed, where successful addressing in one RAM row has been achieved. Error-free operation has been accomplished for all cases under study, with the whole row decoder system’s performance to offer a total power penalty of 2.5 dB.

Keywords

• optical RAM
• optical row decoder
• integrated photonic circuit