Efficient and Power-Aware Design of a Novel Sparse Kogge-Stone Adder using Hybrid Carry Prefix Generator Adder

Abstract

This paper presents a novel Sparse Kogge-Stone adder architecture with a sparsity factor of 2, offering a compelling solution to the challenges faced by parallel prefix adders. The superior performance is achieved by including the hybrid carry prefix generator adder (HCPGA), which leads to the elimination of redundant components, and improvements in power consumption and circuit area without compromising computation speed. The proposed hybrid architecture efficiently generates carry prefixes that negates the need for the conventional generate and propagate block, resulting in reduced computational complexity. The effectiveness of the proposed architecture has been extensively validated using Cadence Virtuoso in the 45nm technology node. In addition to evaluating standard performance parameters such as power, delay, and area, comprehensive Monte Carlo simulations and process corner analyses have been performed to ensure the robustness and reliability of the design. Furthermore, the practical application of the proposed architecture has been demonstrated by integrating it into a digital multiplier architecture, showcasing its potential to enhance the computational capabilities of complex arithmetic circuits. This research contributes to the advancement of efficient adder designs for high-performance computing applications, making it highly beneficial and relevant for modern digital circuit designs.

Keywords

• circuit simulation
• circuit topology
• digital circuits
• parallel architectures
• very large scale integration