Designing a Power and Speed Adaptive 60 GHz Receiver in 22 nm FD-SOI CMOS for Tactile Internet Applications

Abstract

This research presents and examines the first power and speed adaptive 60 GHz receiver, combining the potential of high data rates with low energy consumption. Hence, enabling a range of Tactile Internet applications such as a compact wireless robotic skin. Designed and fabricated in a 22 nm fully depleted silicon-on-insulator (FD-SOI) CMOS process, the required area is only 0.67 mm2. Low energy consumption is achieved by using on-off keying (OOK) and aggressive duty cycling. For data rates up to 25 Mbps, synchronization is achieved by oversampling. In this case, the sampling clock is directly related to the data rate. The duty cycle is generated from the sampling clock and defines the average energy consumption. Consequently, a truly data rate dependent energy consumption can be achieved, which is especially beneficial in low communication load scenarios. At a maximum data rate of 2.8 Gbps, the energy consumption is 15.3 mW, while at 25 kbps the receiver consumes only $\mathrm {1.1~\mu \text {W} }$ . Moreover, the achieved sensitivity is -20.5 dBm at 2.8 Gbps for a bit error rate (BER) below 1E-12 and -25 dBm at 25 kbps respectively.

Keywords

• Adaptive
• duty cycling
• envelope detector
• low noise amplifier (LNA)
• millimeter-wave (mm-wave)
• non-coherent receiver