Design and implementation of hybrid logic based MAC unit using 45 nm technology

Abstract

Digital signal processing algorithms, at times, necessitate the execution of a substantial quantity of mathematical operations to speed up and iterate upon a particular data set. Numerous digital signal processing (DSP) applications impose limitations on delay, necessitating the accomplishment of DSP operations within a predetermined timeframe, hence rendering deferred processing not feasible. Therefore, digital signal processing (DSP) necessitates a multiplier and accumulator (MAC) unit that exhibits fast speed, high throughput, and low power consumption. This research aims to develop and execute a low-power MAC unit utilising a hybrid logic technique to achieve power efficiency. A MAC unit has been purposefully designed with suitable geometries to provide optimised power, area, and delay characteristics. Estimating the delay in the MAC unit depends upon data flow analysis between the MAC blocks, explicitly focusing on low-power concerns. The developed hybrid adder cell possesses several advantageous characteristics, including a high operational speed, low power consumption, minimal transistor count. The MAC architecture uses a 45 nm CMOS technology with the Mentor Graphics tool. This research additionally examines different designs of multipliers and adders that are well-suited for the execution of high throughput signal processing while simultaneously achieving low power consumption. The registers in the MAC have been implemented in GDI logic using Multi Bit Flip flops technique to achieve low power operation. The entire MAC circuitry operates on a voltage supply of 1 V. The hybrid logic MAC architecture that has been developed demonstrates a significant decrease in area consumption, amounting to a reduction of 68 % when compared to the typical CMOS logic design. Hybrid logic demonstrates a power consumption that is 92 % better compared to CMOS logic.

Keywords

• CMOS
• MAC
• Hybrid logic