Theory and Design of Impedance Matching Network Utilizing a Lossy On-Chip Transformer

Abstract

In this paper, we present a study on a transformer-based impedance matching network. We use a simplified transformer model comprising two magnetically coupled coils, which are driven by a source and terminated by a load. The formulae of the load and the source impedance for conjugate matching of both sides of the transformer are presented, and a figure of merit is proposed for the evaluation of the power transfer efficiency of the transformer under conjugate matching conditions. Analytical expressions are provided for constructing the widely used transformer network consisting of a resistive load and a parallel tuning capacitor. To verify the proposed work, we examined various on-chip transformers implemented in 0.18 μm CMOS technology. Simulation and measurement results for a matching network synthesized using the aforementioned analytical expressions corresponded well with the result of analysis for operating frequencies up to 72% of the self-resonant frequency of the transformer. The presented results confirm that the proposed analytical formulae based on the simplified transformer model are useful for the design and optimization of transformer-based impedance matching networks in the microwave and millimeter-wave regimes.

Keywords

• CMOS technology
• impedance matching
• power efficiency
• transformers