Design of Efficient Phase Locked Loop for Low Power Applications

Abstract

The phase-locked loop is a technique that has contributed significantly to technological advancements in many applications in the fast-evolving digital era. In this paper, a Phase Locked Loop (PLL) is designed using 90 nm CMOS technology node with 1.8 V supply voltage. It features a PLL design with minimum power consumption of 194.26 µW with better transient analysis and DC analysis in an analog-to-digital environment. The proposed PLL design provides the best solution for many applications where a PLL is required with high performance but has to be accommodated in less area and low power consumption than state-of-the-art methods. This PLL not only works at high speed but also makes whole system work at low power in a very effective manner, which suits the present digital electronics circuits.

Keywords

• Phase Locked Loop (PLL)
• Phase Frequency Detector/Charge Pump (PFD/CP)
• Low Pass Filter (LPF)
• Current Starved Voltage-Controlled Oscillator (CSVCO)
• Analog Digital Environment (ADE)