FPGA Implementation of an Ant Colony Optimization Based SVM Algorithm for State of Charge Estimation in Li-Ion Batteries

Abstract

Monitoring the State of Charge (SoC) in battery cells is necessary to avoid damage and to extend battery life. Support Vector Machine (SVM) algorithms and Machine Learning techniques in general can provide real-time SoC estimation without the need to design a cell model. In this work, an SVM was trained by applying an Ant Colony Optimization method. The obtained trained model was 10-fold cross-validated and then designed in Hardware Description Language to be run on FPGA devices, enabling the design of low-cost and compact hardware. Thanks to the choice of a linear SVM kernel, the implemented architecture resulted in low resource usage (about 1.4% of Xilinx Artix7 XC7A100TFPGAG324C FPGA), allowing multiple instances of the SVM SoC estimator model to monitor multiple battery cells or modules, if needed. The ability of the model to maintain its good performance was further verified when applied to a dataset acquired from different driving cycles to the cycle used in the training phase, achieving a Root Mean Square Error of about 1.4%.

Keywords

• state-of-charge (SoC) estimation
• battery management
• FPGA
• VHDL
• ant colony optimization (ACO)