Analysis of Multi-Stacked Dielectric Resonator Antenna with Its Equivalent R-L-C Circuit Modeling for Wireless Communication Systems

Abstract

The dielectric resonator antenna (DRA) can be modeled as a series and parallel combination of electrical networks consisting of a resistor (R), inductor (L), and capacitor (C) to address peculiar challenges in antennas suitable for application in emerging wireless communication systems for higher frequency range. In this paper, a multi-stacked DRA has been proposed. The performance and characteristic features of the DRA have been analyzed by deriving the mathematical formulations for dynamic impedance, input impedance, admittance, bandwidth, and quality factor for fundamental and high-order resonant modes. Specifically, the performance of the projected multi-stacked DRA was analyzed in MATLAB and a high-frequency structure simulator (HFSS). Generally, results indicate that variation in the permittivity of substrates, such as high and low, can potentially increase and decrease the quality factor, respectively. In particular, the impedance, radiation fields and power flow have been demonstrated using the proposed multi-stacked electrical network of R, L, and C components coupled with a suitable transformer. Overall, the proposed multi-stacked DRA network shows an improved quality factor and selectivity, and bandwidth is reduced reasonably. The multi-stacked DRA network would find useful applications in radio frequency wireless communication systems. Additionally, for enhancing the impedance, BW of DRA a multi-stacked DRA is proposed by the use of ground-plane techniques with slots, dual-segment, and stacked DRA. The performance of multi-stacked DRA is improved by a factor of 10% as compared to existing models in terms of better flexibility, moderate gain, compact size, bandwidth, quality factor, resonant frequency, frequency impedance at the resonance frequency, and the radiation pattern with Terahertz frequency range.

Keywords

• dynamic impedance
• cut-off frequencies
• bandwidth
• multi-stacked DRA (MSDRA)
• parallel R-L-C circuit
• quality factor