Significant advancements in the field of power electronics have created an ideal opportunity to introduce various topologies of multilevel inverters. These multilevel inverter topologies comprise different notable characteristics, such as staircase sinusoidal output voltage with high quality, a lowered number of power switches, no filter requirement, etc. In this literature, a new asymmetrical MLI topology is proposed to reduce the number of components of the inverter with admirable voltage-step creation. The proposed topology provides a 17-level, staircase-type, nearly sinusoidal output voltage waveform. The number of switches required for the proposed multilevel inverter topology is fewer compared to the existing topology for the same level. A carrier-based sinusoidal pulse-width modulation technique is used for the proposed topology at a switching frequency of 3 kHz. The functioning of the proposed inverter topology is thoroughly examined. A 17-level asymmetrical inverter is executed; both the MATLAB/SIMULINK as well as the experimental results using dSPACE-1103 controller. The simulation results are verified using the experimental results for the proposed 17-level multilevel inverter for modulation indexes of 1 and 0.6.
