The application flow of Stratus HLS tool in high performance double precision floating point multiplication design

Abstract

Double-precision floating-point multiplication parts is one of the most important unit of high performance CPU.This article describes the use of Cadence Stratus HLS tools in 28 nm process design and implement double-precision floating-point multiplication. The frequency of this multiplication is 2.5 GHz, and its area is 28 211 square micrometers, which almost meets the requirements of high performance microprocessor development. The experiences of this work enhance the confidence of the more widely using of the new design methodology in our project.

Keywords

• high-level synthesis
• HLS
• double-precision floating-point multiplication