Journal of Nanotechnology (Jan 2015)

Optimization and Characterization of CMOS for Ultra Low Power Applications

  • Mohd. Ajmal Kafeel,
  • S. D. Pable,
  • Mohd. Hasan,
  • M. Shah Alam

DOI
https://doi.org/10.1155/2015/395090
Journal volume & issue
Vol. 2015

Abstract

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Aggressive voltage scaling into the subthreshold operating region holds great promise for applications with strict energy budget. However, it has been established that higher speed superthreshold device is not suitable for moderate performance subthreshold circuits. The design constraint for selecting Vth and TOX is much more flexible for subthreshold circuits at low voltage level than superthreshold circuits. In order to obtain better performance from a device under subthreshold conditions, it is necessary to investigate and optimize the process and geometry parameters of a Si MOSFET at nanometer technology node. This paper calibrates the fabrication process parameters and electrical characteristics for n- and p-MOSFETs with 35 nm physical gate length. Thereafter, the calibrated device for superthreshold application is optimized for better performance under subthreshold conditions using TCAD simulation. The device simulated in this work shows 9.89% improvement in subthreshold slope and 34% advantage in ION/IOFF ratio for the same drive current.