Real-time acceleration design of Canny algorithm based on Vivado HLS

Abstract

On the shortcomings of Canny edge detection algorithm in the real-time image processing time-consuming and large amount of data for computation, the hardware acceleration method of Canny edge detection algorithm using Vivado HLS is proposed. The method, implemented hardware acceleration, generates the RTL level hardware circuit corresponding to the algorithm of the FPGA logic resources. The results show that the method can quickly detect the edge of the image and effectively reduce the difficulty of FPGA design image algorithm, which can be applied to the real-time video image processing.

Keywords

• image processing
• Vivado HLS
• edge detection; hardware acceleration