Low-latency readout electronics for dynamic superconducting quantum computing

Abstract

Dynamic quantum computing can support quantum error correction circuits to build a large general-purpose quantum computer, which requires electronic instruments to perform the closed-loop operation of readout, processing, and control within 1% of the qubit coherence time. In this paper, we present low-latency readout electronics for dynamic superconducting quantum computing. The readout electronics use a low-latency analog-to-digital converter to capture analog signals, a field-programmable gate array (FPGA) to process digital signals, and the general I/O resources of the FPGA to forward the readout results. Running an algorithm based on the design of multichannel parallelism and single instruction multiple data on an FPGA, the readout electronics achieve a readout latency of 40 ns from the last sample input to the readout valid output. The feedback data link for cross-instrument communication shows a communication latency of 48 ns when 16 bits of data are transmitted over a 2 m-length cable using a homologous clock to drive the transceiver. With codeword-based triggering mechanisms, readout electronics can be used in dynamic superconducting quantum computing.