Low-complexity systolic array structure for field multiplication in resource-constrained IoT nodes

Abstract

Security and privacy issues with Internet of Things (IoT) network make it difficult to use IoT technology. Cryptographic protocols can be put in place on IoT edge nodes to address security flaws. Since the edge nodes have few resources, it is challenging to implement these protocols on them. The key operation in these protocols is finite-field multiplication, and how well it is carried out has a big effect on how well they perform. Therefore, we present in this work a novel irreducible All-One Polynomial (AOP)-based low-complexity bit-serial systolic implementation for multiplication in the binary-extended field. The shown multiplier structure features regular cell architectures and local communication connections between the cells, making it more appropriate for VLSI implementation. When compared to competing multipliers, the complexity analysis of the suggested multiplier reveals a significant savings in area and area-time product. As a result, it is more ideal for cryptographic systems that set additional constraints on area.

Keywords

• Serial multipliers
• Finite field arithmetic
• Crypto-processors
• IoT security
• Systolic arrays
• Embedded computing systems