IEEE Open Journal of Power Electronics (Jan 2024)
Thermal Modeling and Degradation Profiling of E-Mode GaN HEMTs for Aging Characterization
Abstract
Managing the thermal behavior of GaN devices under test (DUT) poses significant challenges during accelerated thermal cycling (ATC) tests, particularly due to the compact packaging of small GaN devices (e.g., QFN package) and the sharp rise in the device's $R_{\rm{DSon}}$ at high junction temperatures. This paper presents a framework for analyzing and modeling the thermal response performance of the ATC test setup and evaluating the impact of non-linear dissipated power on the GaN DUTs. It outlines the limitations of conventional thermal sensors in accurately estimating the DUT's junction temperature through case temperature measurements under ATC conditions. The analysis and modeling of the experimental junction temperature response function shows about 4 s time constant in the measurements using a thermistor placed near the DUT, highlighting the GaN DUT's susceptibility to thermal runaway under ATC conditions ($T_{\rm{j-max}}$ > 125 °C), where the thermal time constant significantly exceeds the DUT's thermal transient time. Consequently, an on-state resistance ($R_{\rm{DSon}}$)-based $T_{\rm{j}}$ estimation method is employed to monitor the $T_{\rm{j}}$ and control the thermal cycling window boundaries effectively. Experimental investigations of several e-mode GaN HEMTs under different ATC windows are conducted to validate the ATC testing framework. Moreover, the temperature coefficient of on-state resistance (α) is characterized and quantified - considering fully packaged individual GaN DUTs’ mechanical and electrical degradation mechanisms.
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