System level modeling of dynamic reconfigurable system-on-chip

Abstract

In this paper methods of dynamically reconfigurable multi-core System-on-chip (SoC) design are discussed, the approaches of system modeling for evaluation of these systems are presented. The dynamically reconfigurable SoC can be developed using the FPGA and the ASIC technologies. The implementations of dynamic reconfiguration using these approaches are essentially different. The system level modeling is used to evaluate the performance of dynamically reconfigured systems in the early stage of their development. The models of dynamically reconfigurable systems have very significant differences from the models of systems without a dynamical reconfiguration. The development of such models may require extensions of existing tools and specification of mechanisms functionality. In this paper the existing tools for SoC system design and the requirements for it to allow modeling of reconfigurable systems are considered. We propose mechanisms for system level modeling of the dynamically reconfigurable Networks-on-Chip (NoC) implemented on the ASIC technology.

Keywords

• System-on-Chip
• Network-on-Chip
• SystemC
• Transaction Level Modeling standard(TLM 2.0)
• System Level Modeling
• Dynamic Reconfigurable System